This invention relates to microcode control memory systems for controlling the central processing unit of a computer system as various program instructions are supplied to it. More particularly, this application relates to a system in which the microcode address sequence for performing a particular program instruction may be altered in progress by sensing conditions in the central processing unit of the computer which will control the microcode instruction sequence.
Certain patents are known to applicant in the prior art which may be relevant to this application. U.S. Pat. No. 3,980,991 shows a system in which a sensed condition is used to control a particular microcode instruction. However, that patent does not anticipate the sophisticated system of the present application.
U.S. Pat. No. 4,079,451 shows a logic means to select the mode of operation of an indirect addressing system between a fast and a slow mode. The fact that the mode of operation is changed dependent upon system conditions may be relevant to the concept of the present invention. Address modification of the type shown in this application is not contemplated by this patent.
U.S. Pat. No. 4,021,779 shows a different type of microprogram control system in which only changes in the control status of the system are stored rather than the complete status for every step in the sequence. Thus, every element of every instruction is not stored when only changes in a condition are stored in memory. This patent is mentioned because it shows the sensing of conditions during a program sequence but the program sequence itself is not altered by the sensed conditions; only the way that the program is stored in memory is altered. U.S. Pat. No. 4,042,972 shows a microprogram system in which sensed conditions are used to cause the skipping of an instruction in a program sequence as the result of a sensed condition, but this patent does not show the altering of microcode instructions in the way contemplated by the present application.
The sensing of operating conditions in a computer system during a microprogrammed instruction sequence is known. However, no prior art known to the present inventor shows the efficiency of microcode memory design accomplished in the present system by using sensed conditions in the computer system to alter the microcode sequence while in operation. Thus, the present invention requires a much smaller microcode memory control system than would be the case if every possible variation and control state had to be specifically preprogrammed into the microcode control memory. The sensing of conditions and alteration of microcode control instruction sequence allows for shorter address length and less microcode memory capacity than would otherwise be the case in a complicated computer system.